An Energy Efficient and Resource Optimal VLSI Architecture for ECG Feature Extraction for Wearable Healthcare Applications

Abstract

The paper presents a low complexity algorithm for extracting features of an electrocardiogram (QRS complex, P wave and T wave). A low power and resource optimal architecture is designed to implement this algorithm efficiently. The algorithm's parameters are chosen appropriately to avoid any floating-point compute-intensive arithmetic operation enabling us to implement it using comparators, shifters and adders only, which leads to efficient hardware resource utilization. The proposed architecture employs techniques such as clock gating to optimize power consumption. The modules delineating different peaks and boundaries of the ECG signal can be turned off when they are not operational or as per the medical requirements. The algorithm and architecture proposed in this paper are validated using MIT-BIH and QT database from Physionet. The proposed algorithm is implemented using the Virtex - 7 FPGA platform with average resource utilization of 0.42%, which is the least compared to other methods. The implementation is synthesized using 180 nm CMOS technology. The proposed design utilizes 7.38 mu W and 7.38 pJ of power and energy respectively, at an operating frequency of 1 MHz at 1.98 V. The energy consumption of the proposed architecture is reduced by factor of 1.28 compared to other known methods due to minimal utilization of Flip-Flops and LUTs. Therefore, our architecture can be efficiently deployed in low power and resource-constrained wearable healthcare applications.