Fakulta elektrotechniky a informatiky / Faculty of Electrical Engineering and Informatics
Stálý URI pro tuto komunituhttps://hdl.handle.net/10195/3847
Práce obhájené před rokem 2008 jsou uloženy pouze v kolekci Vysokoškolské kvalifikační práce
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Konferenční objektpeer-reviewedpostprint Omezený přístup Passage Detection of a Train via a Reference Point(Springer, 2023) Rejfek, Luboš; Pidanič, Jan; Štursa, Dominik; Nguyen, Tan N.; Tran, Phuong T.; Němec, Zdeněk; Zálabský, TomášA reference point detection system for position validation of a mobile object was developed for verification of experiments. The detection is based on a classic image processing algorithm and a processing algorithm using neural networks. Both approaches are compared. High-precision concept of the system is based on a camera sensor and automatic processing of video frames for position evalua-tion. The designed system was tested on a real application proving correct operation.Konferenční objektpeer-reviewedpostprint Omezený přístup Cybersecurity of Sensors on Smart Vehicles: Review of Threats and Solutions(IEEE (Institute of Electrical and Electronics Engineers), 2023) Putro, Prasetyo Adi Wibowo; Amelia, Fetty; Pidanič, Jan; Suhartanto, Heru; Rahardjo, Imam Arif; Imandeka, EjoThe use of sensors in smart vehicles brings benefits and vulnerabilities. Different kinds of sensors in smart vehicles are vulnerable to cyber-attack. Until now, the investigation of challenges and solutions for in-vehicle cybersecurity hasn’t discussed various sensor objects and their correlation. In this study, we studied the cyber security problems of sensors in smart vehicles and how to overcome them. The research was designed as Systematic Literature Review (SLR) using the Kitchenham methodology with modification in the filtering phase using the artificial intelligence application, Elicit, to identify the problems, conclusions, and methodology description. Seventeen publications from 2016 until 2023 were gained from five databases. As a result, we find that the most discussed object related to cybersecurity sensors on smart vehicles are Electronic Control Units. Spoofing and jamming is still the most addressed threat, and machine learning is the most utilized solution to be implemented in detection systems. Advanced detection systems are incorporating updated attack models. We also suggest using updated attack models and machine learning algorithms to ensure the safety and security of smart vehicle technology. All identified sensor technology correlated using mind maps under the Intelligent Transport System theory.Konferenční objektpeer-reviewedpostprint Omezený přístup Analysis of Faculty of Electrical Engineering and Informatics Building Energy Use Intensity in Pardubice(Institute of Physics, 2023) Arif, Rahardjo Imam; Pidanič, Jan; Roleček, Jiří; Garniwa, Iwa; Suhartanto, HeruThe investigation focused on analyzing the energy usage patterns of the Faculty of Electrical Engineering and Informatics in Pardubice. The recorded energy consumption data were examined and discussed. The average heating energy consumption in the Faculty of Electrical Engineering and Informatics building in 2020, 2021, and 2022 is 686.45 MWh or 57% of the total energy equivalent value. Meanwhile, the average electricity consumption in the building during the same period is 518.97 MWh or 43% of the total energy equivalent value. The average fluctuation in heating energy consumption used in the Faculty of Electrical Engineering and Informatics building tends to increase by 2.9% per year, while the average fluctuation in electricity consumption tends to increase by 3.3% per year. According to the findings, the average comprehensive energy consumption per unit area in the building was 146,03kWh/m2. It was the sum of the energy use intensity for heating and the energy use intensity for electricity. The average energy use intensity value for heating in the building was 83.16 kWh/m2, while the average energy use intensity value for electricity was 62.78 kWh/m2.Konferenční objektpeer-reviewedpostprint Omezený přístup IndiRA: Design and Implementation of a Pipelined RISC-V Processor(IEEE (Institute of Electrical and Electronics Engineers), 2023) Tiwari, Ankita; Guha, Prithwijit; Trivedi, Gaurav; Gupta, Nitesh; Jayaraj, Navneeth; Pidanič, JanThe development of Machine Learning and IoT technology requires fast processing. RISC-V is an open-source reduced instruction set-based instruction set architecture, and the processor based on this architecture can be modified accordingly. The base integer instruction extension supports the operating system environment and is also suitable for embedded systems. It is a 32-bit instruction extension and is defined as RV32I. In this paper, we propose a 32-bit integer instruction-based RISC-V processor core. The proposed core has a five-stage pipeline, including the optimized arithmetic and logic unit. The instruction fetch stage is merged with the pre-fetch stage dynamic branch prediction into a two-stage pipeline. The processor is implemented using Verilog HDL, and the resource utilization is verified for FPGA. The results show that the proposed module performs 30% better than the best-performing processor (considering operating frequency) and showed a 17.6% improvement in the proposed core.Konferenční objektpeer-reviewedpostprint Omezený přístup Employing Quantile and Probability Plots for Comparing and Assessing Goodness of Fit for Stochastic Models of the DCT Coefficients of Lossy Compressed Images(IEEE (Institute of Electrical and Electronics Engineers), 2023) Kotov, Dmytro; Fedorov, Oleksii; Omelchenko, Anatolii; Pidanič, Jan; Doležel, PetrThe paper employs probability plots to performgoodness of fit tests for AC DCT coefficients of compressed images. Attention is paid to various probabilistic models of the DCT coefficients, conventional and rarely used. The Laplacian, generalized Gaussian and doubly Gamma distributions comprise the list. A variation of the method of moments, which involves the 2nd and 4th sample moments as well as Sheppard’s corrections to estimate the shape and scale parameters of the distributions is used. Two types of images are considered, namely, texturelike images and those possessing vast regions of monotonicity. Special effort has been put into adjusting the apparatus of the probability plots to make them suitable for dealing with discrete data, in our case with the quantized DCT coefficients of lossy compressed images. As the source of the DCT coefficients, JPEG images are used. This does not lead us to a significant loss of generality: conclusions drawn in this paper remain applicable to a broad variety of formats of lossy compressed images.Konferenční objektpeer-reviewedpostprint (accepted version) Otevřený přístup Design and Implementation of Probabilistic Methods for Spectrum Sensing in Cognitive Radios(IEEE (Institute of Electrical and Electronics Engineers), 2022) Ponomarov, Andrii; Ivanenko, Stanislav; Fedorov, Oleksii; Bezruk, Valeriy; Pidanič, Jan; Doležel, PetrThe paper deals with new unconventional methods of detecting unoccupied frequency channels in cognitive radios. The main feature of these methods consists in their ability of detecting unknown signals in the presence of noise under the condition of a priori uncertainty. It makes it possible to increase the efficiency of detecting unoccupied frequency channels in cognitive radios due to the fact that these methods track changes in the probabilistic properties of observations. During the course of spectrum sensing of the frequency range, the detected signals are divided into known (classified training samples of which are available in the system) and unknown ones. Application of methods for recognizing specified signals in the presence of unknown signals makes it possible to simultaneously avoid the erroneous occupation of a frequency channel by a secondary user, in the case when previously unregistered signal occurs, and also refresh the cognitive radio database. To detect unknown signals, only information about probabilistic characteristics of the channel noise is used.Konferenční objektpeer-reviewedpostprint (accepted version) Otevřený přístup Comparison of Floating-point Representations for the Efficient Implementation of Machine Learning Algorithms(IEEE, 2022) Mishra, Saras Mani; Tiwari, Ankita; Shekhawat, Hanumant Singh; Guha, Prithwijit; Trivedi, Gaurav; Pidanič, Jan; Němec, ZdeněkSmart systems are enabled by artificial intelligence (AI), which is realized using machine learning (ML) techniques. ML algorithms are implemented in the hardware using fixedpoint, integer, and floating-point representations. The performance of hardware implementation gets impacted due to very small or large values because of their limited word size. To overcome this limitation, various floating-point representations are employed, such as IEEE754, posit, bfloat16 etc. Moreover, for the efficient implementation of ML algorithms, one of the most intuitive solutions is to use a suitable number system. As we know, multiply and add (MAC), divider and square root units are the most common building blocks of various ML algorithms. Therefore, in this paper, we present a comparative study of hardware implementations of these units based on bfloat16 and posit number representations. It is observed that posit based implementations perform 1.50x better in terms of accuracy, but consume 1.51x more hardware resources as compared to bfloat16 based realizations. Thus, as per the trade-off between accuracy and resource utilization, it can be stated that the bfloat16 number representation may be preferred over other existing number representations in the hardware implementations of ML algorithms.Konferenční objektpeer-reviewedpostprint (accepted version) Otevřený přístup Design and Implementation of a Low Power Area Efficient Bfloat16 based CORDIC Processor(IEEE, 2022) Mishra, Saras Mani; Shekhawat, Hanumant Singh; Trivedi, Gaurav; Pidanič, Jan; Němec, ZdeněkCoordinate Rotation Digital Computer (CORDIC) algorithm has a great advantage in hardware based implementation because of its simple architecture. It employs shifter and adder for hardware implementation. The major issue with a CORDIC algorithm is the linear dependence of convergence on the number of iterations. Each iteration performs shift and addition or subtraction operations, due to this there is a trade off between area and delay. Also, the floating-point representation of angles would also increase the area and power. The main aim of this work is to implement a low power and area efficient bfloat16 based on a CORDIC algorithm. The proposed hardware module consumes 3.2x and 3.38x less area and power compared to a single-precision floating-point based CORDIC implementation. The result of the proposed module has been verified on a Zynq evaluation FPGA board.Konferenční objektpeer-reviewedpostprint (accepted version) Otevřený přístup A Scalable and Adaptive Convolutional Neural Network Accelerator(IEEE, 2022) Pidanič, Jan; Vyas, Arpan; Karki, Rishav; Vij, Prateek; Trivedi, Gaurav; Němec, ZdeněkMachine learning has become ubiquitous and penetrated every field of technology, medicine, and finance. Convolutional Neural Network (CNN) is one of the most commonly used class of machine learning algorithms that is being used in video and image processing, big data processing, natural language processing, robotics, and a variety of pattern matching and recognition tasks. Depending on the end application, CNNs are being employed on different scales ranging from tiny motion sensors and smartphones to automobiles and server farms. Although existing CNN accelerators are adaptive for different types of CNN models, they are generally suited for a particular scale of operation. In this paper, we describe a scalable and adaptive CNN accelerator. The same hardware-cum-software stack can be configured by a system-level parameter to be synthesized for different scales of operation. This makes the accelerator highly portable across systems of different scales. Furthermore, one single synthesized hardware can run inference for multiple CNN models because of the flexible software stack and hardware control unit making the system highly adaptive. We demonstrate the working of the system at different scales by implementing it on the Xilinx Virtex 7 FPGA and by running multiple CNN models at each scale.Konferenční objektpeer-reviewedpostprint (accepted version) Otevřený přístup An Area and Power Efficient VLSI Architecture to Detect Obstructive Sleep Apnea for Wearable Devices(IEEE, 2022) Parmar, Rushik; Janveja, Meenali; Trivedi, Gaurav; Pidanič, Jan; Němec, ZdeněkSleep disorders are a common detrimental health condition that reduces quality of life. Among different sleep disorders, Obstructive Sleep Apnea (OSA) is one of the most common sleep disorders. OSA is characterized by a reduction or cessation of airflow during sleep. However, due to expensive and cumbersome detection process, only 10% of the OSA cases are actually diagnosed in the real world. To overcome this challenge, an area and power efficient VLSI Architecture for non-invasive detection of OSA, using features of ECG signal and support vector machines (SVM), is proposed in this manuscript. The proposed classifier achieves an accuracy of 84.60% and sensitivity and specificity of 83.85% and 85.58% respectively. The design is further synthesised using 180 nm Bulk CMOS technology consuming 0.46 mu W power at 1 kHz and occupies an area of 0.429 mm(2). The low-power implementation of the proposed design makes it suitable for preventive health wearable devices.
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